Table Of Contents

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Special Section on Networks-on-Chip

Introduction to the Special Section on Networks-on-Chip , Radu Marculescu

Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu (Andy) Wu

Adaptive Channel Buffers in On-Chip Interconnection Networks—A Power and Performance Analysis
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip
Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
Francesco Vitullo, Nicola E. L'Insalata, Esa Petri, Sergio Saponara, Luca Fanucci, Michele Casula, Riccardo Locatelli, Marcello Coppola

A High-Fault-Coverage Approach for the Test of Data, Control, and Handshake Interconnects in Mesh Networks-on-Chip
Érika Cota, Fernanda Lima Kastensmidt, Maico Cassel, Marcos Hervé, Pedro Almeida, Paulo Meirelles, Alexandre Amory, Marcelo Lubaszewski

Secure Memory Accesses on Networks-on-Chip
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, Cristina Silvano

SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip
Dan Zhao, Yi Wang

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
Assaf Shacham, Keren Bergman, Luca P. Carloni

Regular Papers

Efficient Exact Schedulability Tests for Fixed Priority Real-Time Systems
Robert I. Davis, Attila Zabos, Alan Burns

Accurate Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan

Brief Contributions

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^{m})
H. Rahaman, J. Mathew, D.K. Pradhan, A.M. Jabir

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