Table Of Contents
RACE: A Robust Adaptive Caching Strategy for Buffer Cache
Yifeng Zhu, Hong Jiang
Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces
Davy Genbrugge, Lieven Eeckhout
Self-Adaptive Configuration of Visualization Pipeline over Wide-Area Networks
Qishi Wu, Jinzhu Gao, Mengxia Zhu, Nageswara S.V. Rao, Jian Huang, S. Sitharama Iyengar
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies
Zeshan Chishti, T.N. Vijaykumar
Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy Consumption
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
Minimum Deadline Calculation for Periodic Real-Time Tasks in Dynamic Priority Systems
Patricia Balbastre, Ismael Ripoll, Alfons Crespo
Efficient Prefix Updates for IP Router Using Lexicographic Ordering and Updateable Address Set
Sieteng Soh, Lely Hiryanto, Suresh Rai
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
Gunnar Gaubatz, Erkay Savaş, Berk Sunar
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