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IEEE Micro January/February 2008 (Vol. 28, No. 1) ISSN: 0272-1732  

 

Table Of Contents

Micro Economics
The Long Arc Behind Bill Gates' Wealth  Shane Greenstein,  pp. 4-7

Features
Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007  Sarita Adve,  pp. 8-11

Revisiting the Sequential Programming Model for the Multicore Era (Abstract)
Matthew J. Bridges, pp. 12-20

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation Naveen Neelakantam, pp. 21-31

Performance Pathologies in Hardware Transactional Memory  Jayaram Bobba pp. 32-41

MetaTM/TxLinux: Transactional Memory for an Operating System Hany E. Ramadan,  pp. 42-51

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores (Abstract)
Albert Meixner,  pp. 52-59

Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability (Abstract) Xiaoyao Liang,  pp. 60-68

Architecting Efficient Interconnects for Large Caches with CACTI 6.0 (Abstract)
Naveen Muralimanohar, University of Utah pp. 69-79

Toward Ideal On-Chip Communication Using Express Virtual Channels (Abstract)
Amit Kumar, Princeton University pp. 80-90

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching (Abstract)
Moinuddin K. Qureshi, IBM Research pp. 91-98

Virtual Hierarchies  Michael R. Marty,  pp. 99-109

Micro Innovations
A Collaborative IP-Development Session  Philip Emma,  pp. 112, 110-111