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IEEE Design and Test of Computers May-June 2008 (Vol. 25, No. 3)   ISSN: 0740-7475   

Table Of Contents

From the EIC
Effective silicon debug is key for time to money Tim Cheng p. 204

Special Issue Features
Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis Rob Aitken, pp. 206-207

Functional Debug Techniques for Embedded Systems Bart Vermeulen, NXP Semiconductors ,pp. 208-215

In-System Silicon Validation and Debug Miron Abramovici, DAFCA pp. 216-223 

Case Study on Speed Failure Causes in a Microprocessor  Kip Killpack, Intel pp. 224-230

Linking Statistical Learning to Diagnosis Pouria Bastani,  pp. 232-239

Survey of Scan Chain Diagnosis Yu Huang, Mentor Graphics pp. 240-248

Physical Techniques for Chip-Backside IC Debug in Nanotechnologies  Christian Boit,  pp. 250-257

Overview of Debug Standardization Activities Bart Vermeulen, pp. 258-267

Thousand-Core Chips  David Yeh, Texas Instruments pp. 272-278

DATC Newsletter
DATC Newsletter  Joe Damore p. 280

CEDA Currents
CEDA Currents  pp. 282-283

Book Reviews
Learning to assert yourself  Grant Martin, Tensilica pp. 284-285

TTTC Newsletter
TTTC Newsletter  Bruce C. Kim pp. 286-287

The Last Byte
Bugs, moths, grasshoppers, and whales Erik Jan Marinissen, Pp. 288