Table Of Contents
From the EIC
Test compression saves bits, cycles, and money Tim Cheng ,p. 105
Special Issue Features
Guest Editors' Introduction: Progress in Test Compression
Scott Davidson, pp. 112-113
Historical Perspective on Scan Compression
Rohit Kapur, pp. 114-120
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
Laung-Terng Wang, pp. 122-130
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
Chao-Wen Tzeng, pp. 132-140
Hierarchical Test Compression for SoC Designs
Kee Sup Kim, Intel ,Ming Zhang, Intel ,pp. 142-148
RFIC Chips, Part 2
Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers
Ganesh Srinivasan,,pp. 150-159
Wireless System for Microwave Test Signal Generation Qizhang Yin, Monolithic Power Systems ,pp. 160-166
Other Features
An Illustrated Methodology for Analysis of Error Tolerance
Melvin A. Breuer, pp. 168-177
Device Model for Ballistic CNFETs Using the First Conducting Band
Hamidreza Hashempour, pp. 178-186
DATC Newsletter
DATC Newsletter ,Joe Damore ,p. 187
Interview
Discussing DRAM and CMOS Scaling with Inventor Bob Dennard pp. 188-191
Standards
Standards update from IP 07 Victor Berman, Improv Systems,pp. 192-193
Book Reviews
Building your yield of dreams Sachin Sapatnekar, University of Minnesota ,pp. 194-195
CEDA Currents
CEDA Currents ,pp. 196-197
TTTC Newsletter
TTTC Newsletter ,Bruce C. Kim ,pp. 198-199.
The Last Byte
The commonality of vector generation techniques Scott Davidson, Sun Microsystems ,p. 200 |