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IEEE Transaction on Electron Devices Volume: 55  Issue: 6   Date: June 2008
 

Table of Contents

IEEE Transactions on Electron Devices publication information Page(s): C2-C2

What Is in a Page Charge? JINDAL, R. P. , Page(s): 1275-1275

On Common–Base Avalanche Instabilities in SiGe HBTs
Grens, C. M.; Cressler, J. D.; Joseph, A. J. , Page(s): 1276-1285

Bandstructure Effects in Silicon Nanowire Electron Transport
Neophytou, N.; Paul, A.; Lundstrom, M. S.; Klimeck, G. n, Page(s): 1286-1297

Screening Effects Between Field-Enhancing Patterned Carbon Nanotubes: A Numerical Study
Dionne, M.; Coulombe, S.; Meunier, J.-L. , Page(s): 1298-1305

Modeling Thermal Effects in Nanodevices

Raleva, K.; Vasileska, D.; Goodnick, S. M.; Nedjalkov, M. , Page(s): 1306-1316

Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design
Fregonese, S.; Cazin d'Honincthun, H.; Goguet, J.; Maneux, C.; Zimmer, Page(s): 1317-1327

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
Li, H.; Yin, W.-Y.; Banerjee, K.; Mao, J.-F. , Page(s): 1328-1337

Driving Characteristics of a High-Efficacy AC PDP With an Auxiliary Electrode

Choi, K. C.; Jang, C.; Yun, J. B.
Page(s): 1338-1344

Prevention of Boundary Image Sticking in an AC Plasma Display Panel Using a Vacuum Sealing Process
Park, C.-S.; Tae, H.-S.; Kwon, Y.-K.; Heo, E. G.; Lee, B.-H. Page(s): 1345-1351

New Observation of Mobility and Reliability Dependence on Mechanical Film Stress in Strained Silicon CMOSFETs Han, I.-S.; Ji, H.-H.; You, O.-S.; Choi, W.-H.; Lim, J.-E.; Hwang, K.-J.;Page(s): 1352-1358

Characteristic Instabilities in HfAlO Metal–Insulator–Metal Capacitors Under Constant-Voltage Stress
Takeda, K.; Yamada, R.; Imai, T.; Fujiwara, T.; Hashimoto, T.; Ando, T. Page(s): 1359-1365

Lateral Nonuniformity Effects of Border Traps on the Characteristics of Metal–Oxide–Semiconductor Field-Effect Transistors Subjected to High-Field Stresses Tseng, J.-C.; Hwu, J.-G. , Page(s): 1366-1372

Avalanche Breakdown Due to 3-D Effects in the Impact-Ionization MOS (I-MOS) on SOI: Reliability Issues
Mayer, F.; Le Royer, C.; Blachier, D.; Clavelier, L.; Deleonibus, S. , Page(s): 1373-1378

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $hbox{Pr}_{2}hbox{O}_{3}$ Gate Dielectric Pan, T.-M.; Wu, T.-W. , Page(s): 1379-1385

Analytical Electron-Mobility Model for Arbitrarily Stressed Silicon Tan, Y.; Li, X.; Tian, L., Page(s): 1386-1390

MOSFET Performance Scaling—Part I: Historical Trends Khakifirooz, A.; Antoniadis, D. A. , Page(s): 1391-1400

MOSFET Performance Scaling—Part II: Future Directions Khakifirooz, A.; Antoniadis, D. A. , Page(s): 1401-1408

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers Ker, M.-D.; Chang, W.-J. , Page(s): 1409-1416

Comparison of MONOS Memory Device Integrity When Using $hbox{Hf}_{1 - x - y}hbox{N}_{x}hbox{O}_{y}$ Trapping Layers With Different N Compositions Yang, H. J.; Cheng, C. F.; Chen, W. B.;Page(s): 1417-1423

A PSP-Based Small-Signal MOSFET Model for Both Quasi-Static and Nonquasi-Static Operations
Aarts, A. C. T.; Smit, G. D. J.; Scholten, A. J.; Klaassen, D. B. M. , Page(s): 1424-1432

An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation Boeuf, F.; Sellier, M.; Farcy, A.; Skotnicki, T., Page(s): 1433-1440

A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects
Lime, F.; Iniguez, B.; Moldovan, O. , Page(s): 1441-1448

Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS Li, Y.; Yu, S.-M.; Hwang, J.-R,  Page(s): 1449-1455

Three-Dimensional Simulation of Dopant-Fluctuation-Induced Threshold Voltage Dispersion in Nonplanar MOS Structures Targeting Flash EEPROM Transistors Kim, B.; Kwon, W.; Baek, C.-K.; Jin, S.; Song, Page(s): 1456-1463

Trapped-Hole-Enhanced Erase-Level Shift by FN-Stress Disturb in Sub-90-nm-Node Embedded SONOS Memory
Terai, M.; Tsuji, Y.; Kotsuji, S.; Fujieda, S.; Ando, K., Page(s): 1464-1471

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure
Han, J.-W.; Kim, C.-J.; Choi, Y.-K. , Page(s): 1472-1479

Short-Channel Characteristics of Self-Aligned $Pi$-Shaped Source/Drain Ultrathin SOI MOSFETs
Lin, J.-T.; Eng, Y.-C.; Huang, H.-Y.; Kang, S.-S.; Lin, P.-H.; Kao, K.-K.; Lin, J.-D.; Tseng,Page(s): 1480-1486

Statistical Compact Model Parameter Extraction by Direct Fitting to Variations
Takeuchi, K.; Hane, M. , Page(s): 1487-1493

Two-Dimensional Tunneling Effects on the Leakage Current of MOSFETs With Single Dielectric and High- $kappa$ Gate Stacks Luisier, M.; Schenk, A. Page(s): 1494-1501

Hot-Electron Capture for CHEI Programming in SONOS-Type Flash Memory Using High- $k$ Trapping Layer
Zhang, G.; Yoo, W. J.; Ling, C. H. , Page(s): 1502-1510

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM
Lu, Z.; Fossum, J. G.; Zhang, W.; Trivedi, V. P.; Mathew, L.; Sadd, M. , Page(s): 1511-1518

Evaluation of Hot-Electron Effect on LDMOS Device and Circuit Performances
Yuan, J.-S.; Jiang, L. , Page(s): 1519-1523

A MOS Gated Power Semiconductor Switch Using Band-to-Band Tunneling and Avalanche Injection Mechanism Ye, H.; Haldar, P. , Page(s): 1524-1528

Localized Electric Field Mapping in Planar Semiconductor Structures
Andrikopoulos, P.; BooneJr., T. D.; Haegel, N. M. , Page(s): 1529-1534

Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

Vasallo, B. G.; Wichmann, N.; Bollaert, S.; Roelens, Y.; Cappy, A.; Gonzalez, T.; Pardo, Page(s): 1535-1540

Investigation and Modeling of Hot Carrier Effects on Performance of 45- and 55-nm NMOSFETs With RF Automatic Measurement Tang, M.-C.; Fang, Y.-K.; Liao, W.-S.; Chen, D. C.; Yeh, Page(s): 1541-1546

A Statistical Reliability Model for Single-Electron Threshold Logic
Chen, C.; Mao, Y. , Page(s): 1547-1553

The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs
Kumar, M. J.; Siva, M. , Page(s): 1554-1557

Shallow-Trench-Isolation (STI)-Induced Mechanical-Stress-Related Kink-Effect Behaviors of 40-nm PD SOI NMOS Device Su, V. C.; Kuo, J. B.; Lin, I. S.; Lin, G. S.; Chen, D. C.; Yeh, C.-S.; Tsai, C. , Page(s): 1558-1562

First Observation of Bias Oscillations in GaN Gunn Diodes on GaN Substrate
Yilmazoglu, O.; Mutamba, K.; Pavlidis, D.; Karaduman, T. , Page(s): 1563-1567

Insight Into the Aggravated Lifetime Reliability in Advanced MOSFETs With Strained-Si Channels on SiGe Strain-Relaxed Buffers Due to Self-Heating Agaiby, R.; O'Neill, A. G.; Olsen, S. H.; Eneman, Page(s): 1568-1573

2008 EDS Education Award Call for Nominations Page(s): 1574-1574

Interational Semiconductor Conference 31th Edition Page(s): 1575-1575

5th Int. Symp. Advanced Gate Stack Technology (ISAGST) Page(s): 1576-1576

IEEE Transactions on Electron Devices information for authors Page(s): C3-C3