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IEEE Transaction on Electron Devices Volume: 55  Issue: 1   Date: Jan 2008

Table of Contents

Special Issue on Device Technologies and Circuit Techniques for Power Management
Welser, J. J.; Kosonocky, S.; Liu, T.-J. K.; Sakurai, T.; Thewes, R.; Zhao, B.Page(s): 4-7

Metal Electrode/High-$k$ Dielectric Gate-Stack Technology for Power Management
Byoung Hun Lee; Seung Chul Song; Rino Choi; Kirsch, P.Page(s): 8-20

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance
Takagi, S.; Iisawa, T.; Tezuka, T.; Numata, Page(s): 21-39

Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control
Ohtou, T.; Saraya, T.; Hiramoto, T.Page(s): 40-47

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic
Akarvardar, K.; Eggimann, C.; Tsamados Page(s): 48-59

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs ,Tawfik, S.A.; Kursun, V.Page(s): 60-70

Design in the Power-Limited Scaling Regime ,Nikolic, B.Page(s): 71-83

Transistor-and Circuit-Design Optimization for Low-Power CMOS
Mi-Chang Chang; Chih-Sheng Chang; Chih-Ping Chao; Page(s): 84-95

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia
Skotnicki, T.; Fenouillet-Beranger, C.; Gallon, C.; Buf, F Page(s): 96-130

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies
Saxena, S.; Hess, C.; Karbasi, H.;  Page(s): 131-144

Low-Power SRAMs in Nanoscale CMOS Technologies ,Zhang, K.; Hamzaoglu, F.; Yih Wang Page(s): 145-151

Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAM
Mukhopadhyay, S.; Keunwoo Kim; Ching-Te Chuang,Page(s): 152-162

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits
Verma, N.; Kwong, J.; Chandrakasan, A.P.Page(s): 163-174

Nanometer Device Scaling in Subthreshold Logic and SRAM
Hanson, S.; Mingoo Seok; Sylvester, D.; Blaauw, D.Page(s): 175-185

Low Power and Power Management for CMOS—An EDA Perspective
Kawa, J.Page(s): 186-196

Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures
Suhwan Kim; Chang Jun Choi; Deog-Kyoon Jeong; Kosonocky, S.V.; Sung Bae Park Page(s): 197-205

Leakage Suppression of Low-Voltage Transient Voltage Suppressor
Sheng-Huei Dai; Chrong-Jung Lin; Ya-Chin King Page(s): 206-210

Progressive Development of Superjunction Power MOSFET Devices
Yu Chen; Liang, Y.C.; Samudra, G.S.; Xin Yang; Buddharaju, K.D.; Hanhua Feng Page(s): 211-219

Fully Coupled Nonequilibrium Electron–Phonon Transport in Nanometer-Scale Silicon FETs
Rowlette, J.A.; Goodson, K.E.Page(s): 220-232

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation
Fiegna, C.; Yang Yang; Sangiorgi, E.; O'Neill, A.G.Page(s): 233-244

Cool Chips: Opportunities and Implications for Power and Thermal Management
Sheng-Chih Lin; Banerjee, K.Page(s): 245-255

Microwave Performance of Double $delta$-Doped High Electron Mobility Transistor With Various Lower/Upper Planar-Doped Ratio Designs ,Hsien-Chin Chiu; Chung-Wen Chen; Yuan-Chang Huang ,Page(s): 256-2602-

D Analytical Model for Current–Voltage Characteristics and Transconductance of AlGaN/GaN MODFETs
Miao Li; Yan Wang ,Page(s): 261-267

Epitaxial Optimization of 130-nm Gate-Length InGaAs/InAlAs/InP HEMTs for High-Frequency Applications
Malmkvist, M.; Shumin Wang; Grahn, J.V.Page(s): 268-275

Simulation of a Low-Voltage Organic Transistor Compatible With Printing Methods
Takshi, A.; Dimopoulos, A.; Madden, J.D.Page(s): 276-282

A Computational Study of Vertical Partial-Gate Carbon-Nanotube FETs ,Youngki Yoon; Fodor, J.; Jing Guo ,Page(s): 283-288

An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes
Akinwande, D.; Nishi, Y.; Wong, H.-S.P.Page(s): 289-297

Predicting the Performance of Low-Loss On-Chip Inductors Realized Using Carbon Nanotube Bundles
Nieuwoudt, A.; Massoud, Y.Page(s): 298-312

Computational Study of the Ultimate Scaling Limits of CNT Tunneling Devices
Poli, S.; Reggiani, S.; Gnudi, A.; Gnani, E.; Baccarani, G.Page(s): 313-321

A Monothically Integrated Dual-Wavelength Tunable Photodetector Based on a Taper GaAs Substrate
Jihe Lv; Hui Huang; Yongqing Huang; Xiaomin Ren; Ang Miao; Yiqun Li Page(s): 322-328

Hexagonal a-Si:H TFTs: A New Advanced Technology for Flat-Panel Displays
Hojin Lee; Juhn-Suk Yoo; Chang-Dong Kim; In-Byeong Kang; Kanicki, K.Page(s): 329-336

Characterization of Short-Wavelength-Selective a-Si:H MSM Photoconductors for Large-Area Digital-Imaging Applications
Taghibakhsh, F.; Khodami, I.; Karim, K.S.Page(s): 337-342

Hole Distributions in Erased NROM Devices: Profiling Method and Effects on Reliability
Padovani, A.; Larcher, L.; Pavan, P.Page(s): 343-349

Tradeoff Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects
Yokogawa, S.; Kikuta, K.; Tsuchiya, H.; Takewaki, Page(s): 350-357

SiGe HBTs With Normal High-Speed Emitter-Up and Reverse Low-Power Collector-Up Operation
Li Jen Choi; Sibaja-Hernandez, A.; Venegas, R.; Van Huylenbroeck, S.; Decoutere, S.Page(s): 358-364

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations
Hirano, Y.; Tsujiuchi, M.; Maki, Y.; Iwamatsu, T.; Ishii, Y.; Miyanishi, A.; Tsukamoto Page(s): 365-371

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering ,Kasturi, P.; Saxena, M.; Gupta, M.; Gupta, R.S.Page(s): 372-381

Dual-Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part II: Impact of Gate-Dielectric Material Engineering ,Kasturi, P.; Saxena, M.; Gupta, M.; Gupta, R.S.Page(s): 382-387

Statistical Model for Random Telegraph Noise in Flash Memories
Monzio Compagnoni, C.; Gusmeroli, R.; Spinelli, A.S.; Lacaita, A.L.; Bonanomi, M.; Visconti, A.Page(s): 388-395

A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering ,Zhijun Qiu; Zhen Zhang; Ostling, M.; Shi-Li Zhang Page(s): 396-403

A Novel nand Flash Memory With Asymmetric S/D Structure Using Fringe-Field-Induced Inversion Layer
Ki-Tae Park; Jong-Sun Sel; Jungdal Choi; Yunheub Song; Changhyun Kim; Kinam Kim ,Page(s): 404-410

Modeling the Centroid and the Inversion Charge in Cylindrical Surrounding Gate MOSFETs, Including Quantum Effects
Roldan, J.B.; Godoy, A.; Gamiz, F.; Balaguer, M.Page(s): 411-416

Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON
Yasuda, Y.; Tsu-Jae King Liu; Chenming Hu ,Page(s): 417-422

Quantum Modeling of Thermoelectric Properties of Si/Ge/Si Superlattices ,Bulusu, A.; Walker, D.G.Page(s): 423-429

Evaluation of RF-Stress Effect on Class-E MOS Power-Amplifier Efficiency ,Yuan, J.S.; Ma, J.Page(s): 430-434

Analysis of a Narrow-Base Lateral IGBT With Double Buried Layer for Junction-Isolated Smart-Power Technologies
Bakeroot, B.; Doutreloigne, J.; Vanmeerbeek, P.; Moens, P.Page(s): 435-445

Improving the Performance of Superjunction Devices Having Fixed Charge in Isolation and Termination Oxide Layers
Balaji, S.; Karmalkar, S.Page(s): 446-451

Detailed Study of Amorphous Silicon Ultraviolet Sensor With Chromium Silicide Window Layer
Caputo, D.; de Cesare, G.; Nascetti, A.; Tucci, M.Page(s): 452-456

Low-Noise Avalanche Photodiode in Standard 0.35-$mu hbox{m}$ CMOS Technology
Pancheri, L.; Scandiuzzo, M.; Stoppa, D.; Betta, G.-F.D.Page(s): 457-461

Miniature RF Test Structure for On-Wafer Device Testing and In-Line Process Monitoring
Ming-Hsiang Cho; Lee, R.; An-Sam Peng; Chen, D.; Chune-Sin Yeh; Lin-Kun Wu ,Page(s): 462-465

Power Semiconductor Device Figure of Merit for High-Power-Density Converter Design Applications
Hongfang Wang; Wang, F.; Junhong Zhang ,Page(s): 466-470

Special issue on Nanowire Electronics ,Page(s): 471-472

Region 9 Biennial Outstanding Student Paper Award ,Page(s): 473-473

2008 Symposium on VLSI Technology ,Page(s): 474-474

2008 IEEE Radio Frequency Integrated Circuits Symposium ,Page(s): 475-475

IEEE Transactions on Electron Devices information for authors,Page(s): C3-C3