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IEEE Transactions on Circuits and Systems PartII —Volume: 55  Issue: 6   Date: June. 2008

Table of Contents

IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Page(s): C2-C2

Optimal Lossy Matching by Pareto Fronts
Allen, J. C.; Arceo, D.; Hansen, P. , Page(s): 497-501

Single Amplifier Bi-Quadratic Filter Topologies in Transimpedance Configuration
Chandra, G.; Tadeparthy, P.; Easwaran, P. , Page(s): 502-506

Transformer-Coupled Power Amplifier Stability and Power Back-Off Analysis

Chowdhury, D.; Reynaert, P.; Niknejad, A. M. , Page(s): 507-511

Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers
Ge, T.; Chang, J. S. , Page(s): 512-516

Sub-nH Inductor Modeling and Design in 90-nm CMOS Technology for Millimeter-Wave Applications
Hasani, J. Y.; Kamarei, M.; Ndagijimana, F. , Page(s): 517-521

A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells: Application Lenero-Bardallo, J. A.; Serrano-Gotarredona, T.; , Page(s): 522-526

A Tunable Pseudo-Differential OTA With $-78~{hbox {dB}}$ THD Consuming 1.25 mW
Lujan-Martinez, C.; Carvajal, R. G.; Galan, J.; Torralba, , Page(s): 527-531

The Effect of Noise Cross-Coupling on Time-Interleaved Delta-Sigma ADCs
Pamarti, S. , Page(s): 532-536

A Fast and Compact Analog Buffer Design for Active Matrix Liquid Crystal Displays Using Polysilicon Pappas, I.; Siskos, S.; Dimitriadis, C. A. , Page(s): 537-540

Current-Mode Linear Transformation Filters Using Current Mirrors
Souliotis, G.; Psychalinos, C. , Page(s): 541-545

Gated-Clock Design of Linear-Feedback Shift Registers

Aloisi, W.; Mita, R. , Page(s): 546-550

A New Architecture for High-Density High-Performance SGT nor Flash Memory

Kadowaki, T.; Yamakawa, Y.; Nakamura, H.; Kimura, Y.; Page(s): 551-555

Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping
Kim, J.-W.; Kong, B.-S. , Page(s): 556-560

Performance Analysis of Single-Frequency CW Signal-Based I/Q Regeneration in Five-Port Junction- Park, H. C.; Lim, H.-S.; Yu, W.-W. , Page(s): 561-565

Radix-3$,times,$3 Algorithm for The 2-D Discrete Hartley Transform

Wu, J. S.; Shu, H. Z.; Senhadji, L.; Luo, L. M. , Page(s): 566-570

On the Design of Nearly-PR and PR FIR Cosine Modulated Filter Banks Having Approximate Cosine-Rolloff Transition Band Yin, S. S.; Chan, Page(s): 571-575

A Recursive Frequency Estimator Using Linear Prediction and a Kalman-Filter-Based Iterative Algorithm
Zhang, Z. G.; Chan, S. C.; Tsui, K. M. , Page(s): 576-580

Chaos-Coded Modulations Over Rician and Rayleigh Flat Fading Channels
Escribano, F. J.; Lopez, L.; Sanjuan, M. A. F. , Page(s): 581-585

Global Asymptotical Synchronization of Chaotic Lur'e Systems Using Sampled Data: A Linear Matrix Inequality Approach Lu, J.-G.; Hill, D. J. , Page(s): 586-590

Delay-Dependent Approaches to Globally Exponential Stability for Recurrent Neural Networks Shao, H. , Page(s): 591-595

Wiener's Analysis of the Discrete-Time Phase-Locked Loop With Loop Delay
Spalvieri, A.; Magarini, M. , Page(s): 596-600

Time-Domain Modeling of an RF All-Digital PLL
Syllaios, I. L.; Staszewski, R. B.; Balsara, P. T. , Page(s): 601-605

Special issue on Circuits and Systems solutions for nanoscale CMOS design challenges, Page(s): 606-606

IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors, Page(s): 607-607

IEEE Circuits and Systems Society Information, Page(s): C3-C3