Table of Contents

IEEE Transactions on Circuits and Systems—I: Regular Papers publication information
Page(s): C2-C2

Incoming Editorial
Setti, G., Page(s): 477-479

A Low-Voltage Low-Power CMOS Analog Adaptive Equalizer for UTP-5 Cables
Fayed, A. A.; Ismail, M., Page(s): 480-495

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems Mak, P.-I.; U, S.-P.; Martins, R. P.,Page(s): 496-509

A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering Ozalevli, E.; Huang, W.; Hasler, P. E; Anderson, D. V.,Page(s): 510-521

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling
Zanchi, A.; Samori, C., Page(s): 522-534

Phase-Encoding for On-Chip Signalling
D'Alessandro, C. S.; Shang, D.; Bystrov, A.; Yakovlev, A. V. (A.); Maevsky, O.,Page(s): 535-545

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
Dasygenis, M.; Mitroglou, K.; Soudris, D.; Thanailakis, A.,Page(s): 546-558

Contention Resolution—A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications Xu, F.; Chang, C.-H.; Jong, C.-C., Page(s): 559-571

Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design
Zhang, H.; Zhu, J.; Shi, H.; Wang, D., Page(s): 572-585

Hankel-Norm Approximation of IIR by FIR Models: A Constructive Method
Chai, L.; Zhang, J.; Zhang, C.; Mosca, E., Page(s): 586-598

A Balanced Approach to Multichannel Blind Deconvolution
Tsoi, A. C.; Ma, L. S., Page(s): 599-613

Feasibility of Analog Realization of a Sliding-Mode Observer: Application to Data Transmission
L'Hernault, M.; Barbot, J.-P.; Ouslimani, A.,Page(s): 614-624

An $H_{infty}$ Approach for Robust Calibration of Cascaded Sigma–Delta Modulators
Yang, F.; Gani, M., Page(s): 625-634

A Fast Passivity Test for Stable Descriptor Systems via Skew-Hamiltonian/Hamiltonian Matrix Pencil Transformations Wong, N.; Chu, C.-K. , Page(s): 635-643

Optimizations of a Hardware Decoder for Deep-Space Optical Communications
Cheng, M. K.; Nakashima, M. A.; Moision, B. E.; Hamkins, J., Page(s): 644-658

Cell Search in WCDMA Under Large-Frequency and Clock Errors: Algorithms to Hardware Implementation
Li, C.-F.; Chu, Y.-S.; Ho, J.-S.; Sheen, W.-H., Page(s): 659-671

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems
Troya, A.; Maharatna, K.; Krstic, M.; Grass, E.; Jagdhold, U.; Kraemer, R., Page(s): 672-686

Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless HybridDC–DC PWM Converters Axelrod, B.; Berkovich, Y.; Ioinovici, A., Page(s): 687-696

Discontinuous Dynamics of Electric Power System With DC Transmission: A Study on DAE System
Susuki, Y.; Hikihara, T.; Chiang, H.-D., Page(s): 697-707

Corrections to “Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit” [Dec 07 2683-2695] Khan, E.; El-Kharashi, M. W.; Gebali, F.; Abd-El-Barr, M. ,Page(s): 708-708

2008 IEEE Asia Pacific Conference on Circuits and Systems
Page(s): 709-709

IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors
Page(s): 710-710

Put your technology leadership in writing
Page(s): 711-711

IEEE Foundation
Page(s): 712-712

IEEE Circuits and Systems Society Information
Page(s): C3-C3