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IEEE Transactions on Circuits and Systems Part II—Volume: 55  Issue: 1   Date: Jan. 2008
 

Table of Contents

IEEE Transactions on Circuits and Systems—II: Express Briefs publication information ,Page(s): C2-C2

Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers
Pugliese, A.; Cappuccino, G.; Cocorullo, G. Page(s): 1-5

Delta–Sigma D/A Converter Using Binary- Weighted Digital-to-Analog Differentiator for Second-Order Mismatch Shaping
Heng-Yu Jian; Zhiwei Xu; Chang, M.-C.F.Page(s): 6-10

A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control ,Tang, A.; Fei Yuan; Law, E.,Page(s): 11-15

Power-Aware Design of Nanometer MCML Tapered Buffers ,Alioto, M.; Palumbo, G.Page(s): 16-20
Digital Object Identifier 10.1109/TCSII.2007.906983

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers ,Shebaita, A.; Ismail, Y.Page(s): 21-25

Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis ,Guoqing Chen; Friedman, E.G.Page(s): 26-30

A Timing-Driven Approach to Synthesize Fast Barrel Shifters ,Das, S.; Khatri, S.P.Page(s): 31-35

Random Walk Guided Decap Embedding for Power/Ground Network Optimization ,Yici Cai; Le Kang; Jin Shi; Xianlong Hong; Page(s): 36-40

A Signomial Programming Approach for Binary Image Restoration by Penalized Least Squares ,Yijiang Shen; Lam, E.Y Page(s): 41-45

On the Absence of Limit Cycles in State-Space Digital Filters With Minimum $L_{2}$-Sensitivity ,Yamaki, S.; Abe, M.; Kawamata, M.Page(s): 46-50

Integrated Phase-Locking Scheme for SDFT-Based Harmonic Analysis of Periodic Signals ,Sumathi, P.; Janakiraman, P.A.Page(s): 51-55

Analytic Expressions of Two Discrete Hermite–Gauss Signals ,Kong, F.N.Page(s): 56-60

Remarks on $n$ -D Polynomial Matrix Factorization Problems ,Mingsheng Wang ,Page(s): 61-64

Attack Vulnerability of Complex Communication Networks ,Yongxiang Xia; Hill, D.J.Page(s): 65-69

$L(j, , k)$-Labelings of Kronecker Products of Complete Graphs ,Haque, M.E.; Jha, P.K.Page(s): 70-73

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity ,Darabiha, A.; Carusone, A.C.; Kschischang, F.R.Page(s): 74-78

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding ,Ji-Hoon Kim; In-Cheol Park ,Page(s): 79-83

A Compact Single-FPGA Fading-Channel Simulator ,Alimohammad, A.; Fard, S.F.; Cockburn, B.F.; Schlegel, C.,Page(s): 84-88

Synthesis of Cascaded Lossless Commensurate Lines ,Sengul, M.Page(s): 89-91

Power Waves and Conjugate Matching ,Rahola, J.Page(s): 92-96